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cy8c20111, cy8c20121 capsense ? express? ? one button and two button capacitive controllers cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-53516 rev. *g revised june 24, 2011 1. features capacitive button input tied to a configurable output ? robust sensing algorithm ? high sensitivity, low noise ? immunity to rf and ac noise ? low radiated emc noise ? supports wide range of input capacitance, sensor shapes, and sizes target applications ? printers ? cellular handsets ? lcd monitors ? portable dvd players industry's best configurability ? custom sensor tuning ? output supports strong 20 ma sink current ? output state can be controlled through i 2 c or directly from capsense input state ? run time reconfigurable over i 2 c advanced features ? plug-and-play with fact ory defaults ? tuned to support up to 1 mm overlay ? nonvolatile storage of custom settings ? easy integration into existing pr oducts ? configure output to match system ? no external components required ? world class free configuration tool wide range of operating voltages ? 2.45 v to 2.9 v ? 3.10 v to 3.6 v ? 4.75 v to 5.25 v i 2 c communication ? supported from 1.8 v ? internal pull-up resistor support option ? data rate up to 400 kbps. ? configurable i 2 c addressing industrial temperature range: ?40 c to +85 c available in 8-pin soic package 2. overview the capsense ? express? controllers support two capacitive sensing (capsense) buttons and two general purpose outputs in cy8c20121 and one capsense button and one general purpose output in cy8c20111. the device functionality is configured through the i 2 c port and can be stored in on-board nonvolatile memory for automatic loading at power on. the digital outputs are controlled from capsense inputs in factory default settings, but are user configurable for direct control through i 2 c. the four key blocks that make up the cy8c20111 and cy8c20121 controllers are: a robust capacitive sensing core with high immunity against radi ated and conductive noise, control registers with nonvolat ile storage, configurable outputs, and i 2 c communications. the user can configure registers with parameters needed to adjust the operation and sensitivity of the capsense buttons and outputs and permanently store the settings. the standard i 2 c serial communication interface allows the host to configure the device and read sensor information in real time. i 2 c address is fully configurable without any external hardware strapping. [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 2 of 43 3. contents pinouts .............................................................................. 3 typical circuits ................................................................. 4 circuit-1: one button and one led[1] ....... ........... ...... 4 circuit-2: one button and one led with i2c interface ................................................................ 4 circuit-3: two buttons and two leds with i2c interface ................................................................ 5 circuit-4: compatibility with 1.8 v i2c signaling[2] ..... 5 circuit-5: powering down capsense express device for low power requirements .......................... 6 operating modes .............................................................. 6 normal mode ............................................................... 6 setup mode ................................................................. 6 i2c interface ...................................................................... 6 i2c device addressing ........ ........................................ 6 i2c clock stretching .................................................... 7 format for register write and read ........................... 7 registers ........................................................................... 7 output_status ................................................... 10 output_port ........................................................ 10 cs_enable ............................................................. 10 dig_enable ............................................................ 11 set_strong_dm .................................................. 11 op_sel_x ................................................................. 13 logical_opr_inputx .......................................... 13 cs_noise_th ......................................................... 14 cs_bl_upd_th ....................................................... 14 cs_setl_time ........................................................ 14 cs_oth_set ........................................................... 15 cs_hysterisis ...................................................... 15 cs_debounce ....................................................... 16 cs_neg_noise_th ................................................ 16 cs_low_bl_rst .................................................... 16 cs_filtering ......................................................... 17 cs_scan_pos_x .................................................... 17 cs_finger_th_x ................................................... 18 cs_idac_x ............................................................... 18 i2c_addr_lock ....... .............. .............. ........... ....... 18 device_id ............................................................... 19 device_status ..................................................... 19 i2c_addr_dm ........... .............. .............. ........... ....... 20 cs_read_button ................................................. 20 cs_read_blx ......................................................... 21 cs_read_diffx ...................................................... 21 cs_read_rawx ..................................................... 21 cs_read_status ................................................. 22 command_reg ...................................................... 22 layout guidelines and best practices ......................... 24 example pcb layout design with two capsense buttons and two leds ...... .............. 26 operating voltages ......................................................... 27 capsense constraints ................................................... 27 electrical specifications ................................................ 28 absolute maximum ratings ... .................................... 28 operating temperature ............................................. 28 dc electrical characteristics ..................................... 28 dc chip level specifications .................................... 28 dc gpio specifications ............................................ 28 dc por and lvd specifications .............................. 29 dc flash write specifications ................................... 29 dc i2c specifications ........ ....................................... 30 capsense electrical characteristics ......................... 30 ac electrical specifications ....................................... 31 ac chip-level specifications .................................... 31 ac gpio specifications ............................................ 31 ac i 2 c specifications ................................................ 31 examples of frequently used i2c commands ............ 33 ordering information ...................................................... 34 ordering code definitions ..... .................................... 34 thermal impedances ...................................................... 34 solder reflow specifications ........................................ 34 package diagram ............................................................ 35 acronyms ........................................................................ 36 acronyms used .............................................................. 36 document conventions ................................................. 36 units of measure ....................................................... 36 numeric conventions ............ .................................... 36 glossary .......................................................................... 37 document history page ................................................. 42 sales, solutions, and legal information ...................... 43 worldwide sales and design s upport ......... .............. 43 products .................................................................... 43 psoc solutions ......................................................... 43 [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 3 of 43 4. pinouts figure 1. cy8c20111 pin diagram - 8 soic - 1 button table 1. pin definitions ? 8 soic- 1 button figure 2. cy8c20121 pin diagram ? 8 soic- 2 button table 2. pin definitions ? 8 soic- 2 button pin no name description 1v ss ground 2i2c scli 2 c clock 3i2c sdai 2 c data 4 cs0 capsense input 5 nc no connect 6 dig0 digital output 7 nc no connect 8v dd supply voltage pin no name description 1v ss ground 2i2c scli 2 c clock 3i2c sdai 2 c data 4 cs0 capsense input 5 cs1 capsense input 6 dig0 digital output 7 dig1 digital output 8v dd supply voltage [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 4 of 43 5. typical circuits 5.1 circuit-1: one button and one led [1] 5.2 circuit-2: one button and one led with i 2 c interface note 1. the sensors are factory tuned to wo rk with 1 mm plastic or glass overlay. ? ? [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 5 of 43 5.3 circuit-3: two buttons and two leds with i 2 c interface 5.4 circuit-4: compatibility with 1.8 v i 2 c signaling [2] ? ? note 2. 1.8 v v dd _i2c v dd _ce and 2.4 v v dd _ce 5.25 v. [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 6 of 43 5.5 circuit-5: powering down capsense express device for low power requirements for low power requirements, if v dd is to be turned off, the above concept can be used. the v dd s of capsense express, i 2 c pull-ups, and leds must be from the same source. turning off the v dd ensures that no signal is applied to the device while it is unpowered. the i 2 c signals should not be driven high by the master in this situation. if a port pi n or group of port pins can cater to the power supply requirement of the circuit, the ldo can be avoided. 6. operating modes 6.1 normal mode in normal mode of operation, the acknowledgment time is optimized. the timings remain approximately the same for different configurations of the slave. to reduce the acknowl- edgment times in normal mode, the registers 0x07, 0x08, 0x11, 0x50, 0x51, 0x5c, 0x5d are given only read access. writing to these registers can be done only in setup mode. 6.2 setup mode all registers have read and write access (except those which are read only) in this mode. the acknowledgment times are longer compared to normal mode. when capsense scanning is disabled (command code 0x0a in command register 0xa0), the acknowledgment times can be improved to values similar to the normal mode of operation. 7. i 2 c interface the capsense express devices support the industry standard i 2 c protocol, which can be used to: configure the device read the status and data registers of the device control device operation execute commands the i 2 c address can be modified during configuration. 7.1 i 2 c device addressing the device uses a seven bit addressing protocol. the i 2 c data transfer is always initiated by the master sending one byte address; first 7-bit contains address and lsb indicates the data transfer direction. zero in the lsb indicates the write transaction form master and one indicates read transfer by the master. ta b l e 3 shows example for different i 2 c addresses. master or host ldo capsense express i2c pull ups led i2c bus sda scl vdd output output enable table 3. i 2 c addresses 7 bit slave address (in dec) d7 d6 d5 d4 d3 d2 d1 d0 8 bit slave address (in hex) 1 00000010(w) 02 1 0 0 0 0 0 0 1 1(r) 03 75 1 0 0 1 0 1 1 0(w) 96 75 1 0 0 1 0 1 1 1(w) 97 [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 7 of 43 7.2 i 2 c clock stretching ?clock stretching? or ?bus stalling? in i 2 c communication protocol is a state in which the slave holds the scl line low to indicate that it is busy. in this condition, the master is expected to wait until the scl is released by the slave. when an i 2 c master communicates wit h the capsense express device, the capsense express stalls the i 2 c bus after the reception of each byte (that is, just before the ack/nak bit) until processing of the byte is complete and critical internal functions are executed. use a fully i 2 c compliant master to communicate with the capsense express device. an i 2 c master which does not support clock stretching (a bit banged software i 2 c master) must wait for a specific amount of time specified (as shown in the section format for register write and read ) for each register write and read operation before the next bit is transmitted. it is manda tory to check the scl status (it should be high) before i 2 c master initiates any data transfer with capsense express. if the master fails to do so and continues to communicate, the communication is erroneous. the following diagrams represent the ack time delays shown in the register map on page 7. figure 3. write ack time representation figure 4. read ack time representation 7.3 format for register write and read register write format. register read format. legends : 8. registers table 4. register conventions start slave addr + w areg addr adata adata a . . . . . data a stop start slave addr + w areg addr astop start slave addr + r a data a data a . . . . . data nstop master a - ack slave n- nak convention description rw register have both read and write access r register have only read access wpr write register with pass code fd factory defaults [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 8 of 43 table 5. register map name register address (in hex) access writable only in setup mode [3] factory default values of registers (in hex) i 2 c max ack time in normal mode (ms) [5] i 2 c max ack time in setup mode (ms) [5] page no. 1 button 2 button output_port 04 w 01 03 0.10 10 cs_enable 07 rw yes 01 03 11 10 dig_enable 08 rw yes 01 03 11 11 set_strong_dm 11 rw yes 01 03 11 11 op_sel_0 1c rw 82 82 0.12 11 13 logical_opr_input0 1e rw 01 01 0.12 11 13 op_sel_1 [4] 21 rw 82 0.12 11 13 logical_opr_input1 [4] 23 rw 02 0.12 11 13 cs_noise_th 4e rw 28 28 0.11 11 14 cs_bl_upd_th 4f rw 64 64 0.11 11 14 cs_setl_time 50 rw yes a0 a0 35 14 cs_oth_set 51 rw yes 00 00 35 15 cs_hysterisis 52 rw 0a 0a 0.11 11 15 cs_debounce 53 rw 03 03 0.11 11 16 cs_neg_noise_th 54 rw 14 14 0.11 11 16 cs_low_bl_rst 55 rw 14 14 0.11 11 16 cs_filtering 56 rw 20 20 0.11 11 17 cs_scan_pos_0 5c rw yes 00 00 11 17 cs_scan_pos_1 [4] 5d rw yes 01 11 17 cs_finger_th_0 66 rw 64 64 0.14 11 18 cs_finger_th_1 [4] 67 rw 64 0.14 11 18 cs_idac_0 70 rw 0a 0a 0.14 11 18 cs_idac_1 [4] 71 rw 0a 0.14 11 18 i2c_addr_lock 79 rw 01 01 0.11 11 18 device_id 7a r 11 21 0.11 11 19 device_status 7b r 03 03 0.11 11 19 i2c_addr_dm 7c rw 80 80 0.11 11 20 cs_read_button 81 rw 81 81 0.12 11 20 cs_read_blm 82 r na na 0.12 11 21 cs_read_bll 83 r na na 0.12 11 21 cs_read_diffm 84 r na na 0.12 11 21 cs_read_diffl 85 r na na 0.12 11 21 cs_read_rawm 86 r na na 0.12 11 21 cs_read_rawl 87 r na na 0.12 11 21 cs_read_status 88 r na na 0.12 11 22 command_reg a0 w 00 00 0.10 11 22 notes 3. these registers are writable only after entering into setup mode. all other registers are available for read and write in nor mal and setup mode. 4. these registers are available only in cy8c20121 device. 5. the ack times specified are 1x i2c ack times. [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 9 of 43 table 6. capsense express commands command [6] description executable mode duration the device is not ac- cessible after ack (in ms) [5] w 00 a0 00 get firmware revision setup/normal 0 w 00 a0 01 store current config uration to nvm setup/normal 120 w 00 a0 02 restore factory c onfiguration setup/normal 120 w 00 a0 03 write nvm por defaults setup/normal 120 w 00 a0 04 read nvm por defaults setup/normal 5 w 00 a0 05 read current configurations (ram) setup/normal 5 w 00 a0 06 reconfigure device (por) setup 5 w 00 a0 07 set normal mode of operation setup/normal 0 w 00 a0 08 set setup mode of operation setup/normal 0 w 00 a0 09 start scan setup/normal 10 w 00 a0 0a stop scan setup/normal 5 w 00 a0 0b get capsense scan status setup/normal 0 note 6. ?w? indicates the write transfer. the next byte of data represents the 7 bit i 2 c address. [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 10 of 43 8.1 output_status output status register output_status: 00h the output status register represents the actual logical levels on the output pins. 8.2 output_port output port register output_port: 04h this register is used to write data to dig output port. pins defined as output of co mbinational logic (in op_sel_x register) ca nnot be changed using this register. 8.3 cs_enable select capsense input register cs_enable: 07h ( writable only in setup mode) 1 button76543210 access: fd r:01 bit name sts[0] 2 button76543210 access: fd r:03 bit name sts[1:0] bit name description 1:0 sts [1:0] used to represent the output status 0 output low 1 output high 1 button76543210 access: fd w:01 bit name dig[0] 2 button76543210 access: fd w:03 bit name dig[1:0] bit name description 1:0 dig [1:0] a bit set in this register sets the logic level of the output. 0 logic ?0? 1 logic ?1? 1 button76543210 access: fd rw:01 bit name cs[0] 2 button76543210 access: fd rw:03 bit name cs[1:0] [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 11 of 43 this register is used to enable capsense inputs. this register should be set before setting finger threshold (0x66, 0x67) and idac setting (0x70, 0x71) registers. 8.4 dig_enable select dig output register gpo_enable: 08h (writable only in setup mode) this register is used to enable dig (dig ital) outputs. if dig output is enabled, the strong drive mode register (11h) should al so be set. if dig output is disabled the drive mode of these pins is high z. 8.5 set_strong_dm sets strong drive mode for dig outputs. set_strong_dm: 11h (writable only in setup mode) this register sets strong drive mode for dig (digital) outputs. to set strong drive mo de the pin should be enabled as gp output . bit name description 1:0 cs [1:0] these bits are used to enable capsense inputs. 0 disable capsense input 1 enable capsense input 1 button76543210 access: fd rw:01 bit name dig[0] 2 button76543210 access: fd rw:03 bit name dig [1:0] bit name description 1:0 dig [1:0] these bits are used to enable dig outputs. 0 disable dig output 1 enable dig output 1 button76543210 access: fd rw:01 bit name dm [0] 2 button76543210 access: fd rw:03 bit name dm [1:0] bit name description 1:0 dm [1:0] these bits are used to set the strong drive mode to dig outputs. 0 strong drive mode not set 1 strong drive mode set [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 12 of 43 figure 5. cy8c20111 digital logic diagram figure 6. cy8c20121 digital logic diagram inversion logic dig0 op_sel_0 [0] op_sel_0 [1] logical_opr_input0 [0] op_sel_0 [7] and / or logic selection a b s output_port [0] enb cs0 inversion logic digx op_sel_x [0] op_sel_x [1] and / or logic selection a b s logical_opr_inputx [0] logical_opr_inputx [1] input selection logic op_sel_x [7] and / or logic selection a b s output_port [x] enb enb cs0 cs1 [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 13 of 43 8.6 op_sel_x logic operation selection registers this register is used to enable logic operation on gp outputs. op_sel_0 should be configured to get the logic operation output on dig0 output and op_sel_1 for dig1 output. wr ite to these registers during the disable st ate of respective di g output pins does not have any effect. the input to the logic operation can be sele cted in logic_oprx registers. the selected in puts can be ored or anded. the output of logic operation can also be inverted. 8.7 logical_opr_inputx selects input for logic operation logical_opr_input0: 1eh logical_opr_ input1: 23h (not available for 1 button) logical_opr_input0 logical_opr_input1 these registers are used to give the input to logic operation block. the inputs can be only capsense input status. op_sel_0: 1ch op_sel_1: 21h (not available for 1 button) 1/2button76543210 access: fd rw: 0 rw: 0 rw: 0 bit name op_en invop operator bit name description 7 op_en this bit enables or disables logic operation. 0 disable logic operation 1 enable logic operation 1 invop this bit enables or disabl es logic operation output inversion. 0 logic operation output not inverted 1 logic operation output inverted 0 operator this bit selects which operator should be used to com pute logic operation. 0 logic operator or is used on inputs 1 logic operator and is used on inputs 1 button76543210 access: fd rw:01 bit name csl[0] 2 button76543210 access: fd rw:01 bit name csl [1:0] 2 button76543210 access: fd rw:02 bit name csl [1:0] bit name description 1:0 csl [1:0] these bits select s the input for logic operation block. [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 14 of 43 8.8 cs_noise_th noise threshold register cs_noise_th: 4eh this register sets the noise threshold value. for individual se nsors, count values above this threshold do not update the basel ine. this count is relative to baseline. this parameter is common for all sensors. the range is 3 to 255 and it should satisfy the equation nt < mi n (finger threshold ? hysteresis ? 5). recommended value is 40% of finger threshold. 8.9 cs_bl_upd_th baseline update threshold register cs_bl_upd_th: 4fh when the new raw count value is above the current baseline and the difference is below the noise threshold, the difference betw een the current baseline and the raw count is accumulated into a ? bucket.? when the bucket fills, the baseline increments and the b ucket is emptied. this parameter sets the threshold that the bucket mu st reach for the baseline to increment. in other words, lower v alue provides faster baseline update rate and vice ve rsa. this parameter is common for all sensors. the range is 0 to 255. 8.10 cs_setl_time settling time register cs_setl_time: 50h (writable only in setup mode) the settling time parameter controls the duration of the capacit ance-to-voltage conversion phase. the parameter setting control s a software delay that allows the voltage on the integrating capacitor to stabilize. this parameter is common for all sensors. this register should be se t before setting finger thr eshold (0x66, 0x67) and idac setting (0x70, 0x71) registers. the range is 2 to 255. 1/2 button 7 6 5 4 3 2 1 0 access: fd rw:28 bit name nt[7:0] bit name description 7:0 nt [7:0] these bits are used to set the noise threshold value. 1/2 button76543210 access: fd rw:64 bit name blut[7:0] bit name description 7:0 blut [7:0] these bits set the threshold that t he bucket must reach for baseline to increment. 1/2 button76543210 access: fd rw:a0 bit name stlng_tm[7:0] bit name description 7:0 stlng_tm [7:0] these bits are used to set the settling time value. [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 15 of 43 8.11 cs_oth_set capsense clock select, sensor auto reset register cs_oth_set: 51h (writable only in setup mode) the registers set the capsense module frequency of oper ation and enables or disables the sensor auto reset. cs_clk bits provides option to select vari able clock input for the capsense block. a s ensor design having higher paratactic req uires lower clock for better performance and vice versa. sensor auto reset determines whether the baseline is updated at all times or only when the signal difference is below the noise threshold. when set to ?1? (enabled), the baseline is updated constantly. this setting limits th e maximum time duration of the sensor, but it prevents the sensors from permanently turning on when the raw count suddenly rises with out anything touching the sensor. this sudden rise can be caused by a large power supply voltage fluc tuation, a high energy rf noise so urce, or a very quick temperatu re change. when the parameter is set to ?0? (disabled), the baseline is updated only when raw count and baseline difference is bel ow the noise threshold parameter. this parameter may be enabled unle ss there is a demand to keep the sensors in the on state for a long time. this parameter is common for all sensors. 8.12 cs_hysterisis hysteresis register cs_hysterisis: 52h the hysteresis parameter adds to or subtracts from the finger th reshold depending on whether the sensor is currently active or inactive. if the sensor is off, the differ ence count must overcome the ?finger thresh old + hysteresis?. if the sensor is on, th e difference count must go below the ?finger threshold ? hysteresis?. it is used to add debouncing and ?sticki ness? to the finger detection algorithm. this parameter is common for all sensors. possible values are 0 to 255. however, the setting must be lowe r than the finger threshold parameter setting. recommended value for hysteresis is 15 percent of finger threshold. 1/2 button76543210 access: fd rw: 00 rw: 0 bit name cs_clk[1:0] sns_ar bit name description 6:5 cs_clk[1:0] these bits selects the capsense clock. 3 sns_ar this bit is used to enable or disable sensor auto reset. 0 1 disable sensor auto reset enable sensor auto reset cs_clk[1:0] frequency of operation 00 imo 01 imo/2 10 imo/4 11 imo/8 1/2 button76543210 access: fd rw:0a bit name hys[7:0] bit name description 7:0 hys [7:0] these bits are used to set the hysteresis value. [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 16 of 43 8.13 cs_debounce debounce register. cs_debounce: 53h the debounce parameter adds a debounce counter to the ?sensor acti ve transition?. for the sensor to transition from inactive to active, the consecutive samples of differ ence count value must stay above the ?finger th reshold + hysteresis? for the number specified. this parameter is commo n for all sensors. possible values are 1 to 255. a se tting of ?1? provides no debouncing. 8.14 cs_neg_noise_th negative noise threshold register cs_neg_noise_th: 54h this parameter adds a negative difference count threshold. if the current raw count is below the baseline and the difference be tween them is greater than this thres hold, the baseline is not updated. however, if th e current raw count stays in the low state (dif ference greater than the threshold) for the number of samples specified by the low baseline reset parameter, the baseline is reset. thi s parameter is commo n for all sensors. 8.15 cs_low_bl_rst low baseline reset register cs_low_bl_rst: 55h this parameter works together with the negat ive noise threshold parameter. if the sample count values are below the baseline mi nus the negative noise threshold for t he specified number of samples, the baseline is set to the new raw count value. it essentiall y counts the number of abnormally low samples required to reset the basel ine. it is generally used to co rrect the finger-on-at-startup c ondition. this parameter is common for all sensors. 1/2 button76543210 access: fd rw:0a bit name db[7:0] bit name description 7:0 db [7:0] these bits are used to set the debounce value. 1/2 button76543210 access: fd rw:0a bit name nnt[7:0] bit name description 7:0 nnt [7:0] thes e bits are used to set the negative noise value. 1/2 button76543210 access: fd rw:0a bit name lbr[7:0] bit name description 7:0 lbr [7:0] these bits are used to set the low baseline reset value. [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 17 of 43 8.16 cs_filtering capsense filtering register cs_filtering: 56h this register provides an option for forc ed baseline reset and to enable and configure two different types of software filters. 8.17 cs_scan_pos_x scan position registers cs_scan_pos_0: 5ch (writable only in setup mode) cs_scan_pos_1: 5dh (not available for 1 button) (writable only in setup mode) this register is used to set the position of the sensors in the switch table for proper scanning sequence because the capsense sensors are scanned in sequence. this register should be set after setting 0x07, 0x50, and 0x51 registers. 1/2 button76543210 access: fd rw: 0 rw: 1 rw: 0 rw: 00 bit name rstbl i2c_ds avg_en avg_order[1:0] bit name description 7 rstbl this bit resets all the baselines and it is auto cleared to ?0?. 0 all baselines are not reset 1 all baselines are reset 5 i2c_ds when this bit is set to ?1? the capsense scan sample is dropped if i 2 c communication was active during scanning. 0 disable the i 2 c drop sample filer 1 enable the i 2 c drop sample filter 4 avg_en this bit enables average filter on raw counts. 0 disable the average filter 1 enable the average filter [1:0] avg_order[1:0] these bits are used to select the number of capsense samples to average: avg_order[1:0] in hex samples to average 00 2 01 4 10 8 11 16 1/2 button7654321 0 access: fd rw: 0 bit name scan_pstn 2 button7654321 0 access: fd rw: 1 bit name scan_pstn bit name description 0 scan_pstn this bit sets the scan position. [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 18 of 43 8.18 cs_finger_th_x finger threshold registers this register sets the finger threshold value for capsense inputs . possible values are 3 to 255. this parameter should be confi gured individually for each capsense inputs. this register should be set after setting 0x07, 0x50, and 0x51 registers. 8.19 cs_idac_x idac setting registers cs_idac_0: 70h cs_idac_1: 71h (not available in 1 button) the idac register controls the sensitivity of the capsense algorithm. this regi ster is used to tune the capsense input for spec ific design or overlays. decreasing the value of this register increa ses the sensitivity of the capsen se buttons and vice versa. dec reasing the value of idac increases noise and vice versa. possible values are 1 to 255. if the value is set to 0 then the value is reset to default value 10. the recommended value is greater than 4. setting value 4 creates excessive amount of noise. this register should be set after setting 0x07, 0x50, and 0x51 registers . 8.20 i2c_addr_lock i2c address lock registers i2c_addr_lock: 79h this register is used to unlock and lock the i 2 c address register (7ch ) access. the device i 2 c address should be modified by writing new address to register 7ch after unlocking the access using this register. write to the 7c regist er during the locked state do es not have any effect and the new address take effect only after the access is locked. to lock or unlock the i 2 c al bit, the following three byte s must be written to register 79h: unlock i2cal: 3ch a5h 69h lock i2cal: 96h 5ah c3h reading the i2cal bit from register 79h indicates the current access state. cs_finger_th_0: 66h cs_finger_th_1: 67h (not available in 1 button) 1/2 button76543210 access: fd rw: 64 bit name ft[7:0] bit name description [7:0] ft [7:0] these bi t set the finger threshold for capsense inputs. 1/2 button76543210 access: fd rw: 0a bit name idac[7:0] bit name description [7:0] idac [7:0] these bit set the idac values. 1/2 button76543210 access: fd wpr: 0 bit name i2cal bit name description 0 i2cal this bit gives the lock/unlock status of i 2 c address. 0unlocked 1 locked [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 19 of 43 8.21 device_id device id register device_id: 7ah this register contains the device and product id. the device and product id corresponds to ?xx? in cy8c201xx. 8.22 device_status device status register device_status: 7bh this register contains the device status. 1 button76543210 access: fd r: 11 bit name dev_id[7:0] 2 button 7 6 5 4 3 2 1 0 access: fd r: 21 bit name dev_id[7:0] bit name description 7:0 dev_id [7:0] these bits contain the device and product id. part no device/product id cy8c20111 11 cy8c20121 21 1/2 button 7 6 5 4 3 2 1 0 access: fd r : 00 r: 0 r : 0 r: 0 r: 0 r: 0 bit name ip_volt[1:0] ires load_fd no_nvm_wr cse dige bit name description 7:6 ip_volt [1:0] supply voltage is automatical ly detected and these bits are set accordingly. 5 ires when set to ?1?, this bit indicates that an internal reset occurred. 0 indicates the last system reset was not internal reset 1 indicates the last system reset was internal reset 4 load_fd this bit indicates whether factory defaults are loaded during power-up. 0 user default configuration is loaded during power-up 1 factory default configuration is loaded during power-up 3 no_nvm_wr when set to ?1?, this bit indicates th at the supply voltage applied to the device is too low for a write to nonvolatile memory operat ion, and no write is performed. this bit must be checked before any store or write por command. 1 cse this bit indicates whether capsen se function is enabled or disabled. 0 functionality of capsense block is disabled 1 functionality of capsense block is enabled 0 dige this bit indicates whether gp ou tput function is enabled or disabled. 0 functionality of digital output block is disabled 1 functionality of digital output block is enabled ip_volt[1:0] supply voltage 00 5 01 3.3 10 2.7 11 reser ed [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 20 of 43 8.23 i2c_addr_dm device i 2 c address and i 2 c pin drive mode register i2c_addr_dm: 7ch this register sets the drive mode of i 2 c pins and i 2 c slave address. to write to this register, register 79h must first be unlocked. the value written to register 7ch is applied only after locking register 79h again. 8.24 cs_read_button button select register i2c_addr_dm : 81h the scan result of a capsense input (raw count, difference count, and baseline) can be read only for one input at a time using 82h-87h registers. this register is used to select a capsense input to read the raw count, difference count, and baseline. only the pin s defined as capsense inputs in register 07h can be used with this regist er. trying to select other pins not defined as capsense does not have any change. 1 button76543210 access: fd rw: 0 rw: 00 bit name i2cip_en i2c_addr[6:0] bit name description 7 i2cip_en this bit is used to set the i 2 c pins drive mode. 0 internal pull-up enabled 1 internal pull-up disabled 6:0 i2c_addr [6:0] used to set the device i 2 c address. 1 button76543210 access: fd rw: 0 rw: 0 bit name rd_en csbn[0] 2 button76543210 access: fd rw: 0 rw: 00 bit name rd_en csbn[1:0] bit name description 7 rd_en this bit enables the capsense raw data reading. 0 disable capsense scan result reading 1 enable capsense scan result reading 1:0 csbn [1:0] these bits decide which capsense but ton scan result are read. when writing to this register, the bitmask must contain only one bit set to ?1?, otherwise the data is discarded. csbn [1:0] capsense button no 01 1 10 2 [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 21 of 43 8.25 cs_read_blx baseline value msb/lsb registers reading from this register returns the 2-byte curr ent baseline value for the selected capsense input. 8.26 cs_read_diffx difference count value msb/lsb registers reading from this register returns the 2-byte curr ent difference count for the selected capsense input. 8.27 cs_read_rawx difference count value msb/lsb registers reading from this register returns the 2-byte curren t raw count value for the selected capsense input. cs_read_blm: 82h cs_read_bll: 83h 1/2 button76543210 access: fd r: 00 bit name bl [7:0] bit name description 7:0 bl [7:0] these bits represent the baseline value. cs_read_diffm: 82h cs_read_diffl: 83h 1/2 button76543210 access: fd r: 00 bit name dif [7:0] bit name description 7:0 dif [7:0] these bits represent the sensor difference count. cs_read_rawm: 82h cs_read_rawl: 83h 1/2 button76543210 access: fd r: 00 bit name rc [7:0] bit name description 7:0 rc [7:0] these bits represent the raw count value. [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 22 of 43 8.28 cs_read_status sensor on status register cs_read_status: 88h this register gives the sensor on/off status. a bit ?1? indicates sensor is on and ?0? indicates sensor is off. 8.29 command_reg command register command_reg: a0h commands are executed by writing the command code to the command register. 1 button76543210 access: fd r: 0 bit name bt_st[0] 2 button76543210 access: fd r: 00 bit name bt_st[1:0] bit name description 1:0 bt_st [1:0] these bits used to represent sensor status. 0 sensor off 1 sensor on 1/2 button76543210 access: fd w: 00 bit name cmnd [7:0] bit name description 7:0 cmnd [7:0] refer to the followi ng table for command register opcodes. command code name description 00h get firmware revision the i 2 c buffer is loaded with the one byte firmware revision value. reading one byte after writing this command returns the firmware revision. the upper nibble of the firmware revision byte is the major revision number and the lower nibble is the minor revision number. 01h store current configu- ration to nvm the current register settings are saved in n onvolatile memory (flash). this setting is automatically loaded after the next device reset/power-up or if the reconfigure device (06h) command is issued. 02h restore factory configuration replaces the saved user conf iguration with the factory def ault configuration. current settings are unaffected by this command. new settings are loaded after the next device reset/power-up or if the 06h command is issued. 03h write por defaults sends new power-up defaults to the capsense controller without changing current settings unless the 06h command is issued afterwards. this command is followed by 123 data bytes according to the por default data structure table. the crc is calculated as the xor of the 122 data bytes (00h-79h). if the crc check fails or an incomplete block is sent, the slave responds with an ack and the data is not saved to flash. to define new por defaults: write command 03h write 122 data bytes with new values of r egisters (use the _flash.iic file generated from s/w tool) write one crc byte calculated as xor of previous 122 data bytes [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 23 of 43 04h read por defaults reads the por settings stored in the nonvolatile memory. to read por defaults: write command 04h read 122 data bytes read one crc byte 05h read device configu- ration (ram) reads the current device configuration. give s the user "flat-address-space" access to all device settings. to read device configuration: write command 05h read 122 data bytes read one crc byte 06h reconfigure device (por) immediately reconfigures the device with actu al por defaults from flash. has the same effect on the registers as a por. this comma nd can only be executed in setup operation mode (command code 08). 07h set normal operation mode sets the device in normal operation mode. in this mode, capsense pin assignments cannot be modified; settling time, idac setting, external capacitor, and sensor auto-reset also cannot be modified. 08h set setup operation mode sets the device in setup operation mode. in this mode, capsense pin assignments can be changed along with other parameters. 09h start capsense scanning allows the user to start csa scanning after it has been stopped using command 0x0a. note that at por, scanning is enabled and star ted by default if one or more sensors are enabled. 0ah stop capsense scanning allows the user to stop csa scanning. a system host controller might initiate this command before powering down the device to make sure that during power-down no capsense touches are detected. when csa scanning is stopped by the user and the device is still in the valid v cc operating range, the following behavior is supported: any change to configuration can still be done (as long as v cc is in operating range). command code 0x06 overrides the status of stop/scan by enabling and starting csa scanning if one or more sensors are enabled. capsense read-back values return 0x00. 0bh returns capsense scanning status the i 2 c buffer is loaded with the one-byte csa scanning status value. after writing the value 0bh to the a0h register, reading one byte returns the csa scanning status. it returns the lvd_stop_scan and stop_scan bits. lvd_stop_scan is bit 3 - set when csa is stopped because v cc is outside the valid operating range. stop_scan is bit 2 - set when csa is stopped by the user by writing command 0x0a. command code name description [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 24 of 43 9. layout guidelines and best practices the recommended maximum overlay thickne ss is 2 mm. for more details refer to an53490 , section the integrating capacitor. sl. no. category min max recommendations/remarks 1 button shape solid round pattern, round with led hole, rectangle with round corners 2 button size 5 mm 15 mm 10 mm 3 button button spacing = button ground clearance 8 mm 4 button ground clearance 0.5 mm 2 mm button ground clearance = overlay thickness 5 ground flood - top layer hatched ground 7 mil trace and 45 mil grid (15% filling) 6 ground flood - bottom layer hatched ground 7 mil trace and 70 mil grid (10% filling) 7 trace length from sensor to psoc - buttons 200 mm < 100 mm. 8 trace width 0.17 mm 0.20 mm 0.17 mm (7 mil) 9 trace routing traces should be routed on the non sensor side. if any non capsense trace crosses capsense trace, ensure that inter- section is orthogonal. 10 via position for the sensors via should be pl aced near the edge of the button/slider to reduce trace length thereby increasing sensitivity. 11 via hole size for sensor traces 10 mil 12 no. of via on sensor trace 1 2 1 13 capsense series resistor placement 10mm place capsense series resistors close to psoc for noise suppression.capsense resistors have highest priority place them first. 14 distance between any capsense trace to ground flood 10 mil 20 mil 20 mil 15 device placement mount the device on the layer opposite to sensor. the capsense trace length between the device and sensors should be minimum 16 placement of components in 2 layer pcb top layer-sensor pads and bottom layer-psoc, other compo- nents and traces. 17 placement of components in 4 layer pcb top layer-sensor pads, second layer ? capsense traces, third layer-hatched ground, bottom layer- psoc, other components and non capsense traces 18 overlay material should to be non co nductive material. glass, abs plastic, formica 19 overlay adhesives adhesive should be non conductive and dielectrically homog- enous. 467mp and 468mp adhesives made by 3m are recommended. 20 led back lighting cut a hole in the sensor pad and use rear mountable leds. refer example pcb layout design with two capsense buttons and two leds on page 26. 21 board thickness standard board thickness for capsense fr4 based designs is 1.6 mm. [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 25 of 43 figure 7. button shapes figure 8. button layout design x: button to ground clearance y: button to button clearance figure 9. recommended via-hole placement ? ? [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 26 of 43 9.1 example pcb layout design with two capsense buttons and two leds figure 10. top layer figure 11. bottom layer ? ? [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 27 of 43 10. operating voltages for details on i2c 1x ack time, refer register map on page 7 and capsense express commands on page 8. i2c 4x ack time is approximately four times the val ues mentioned in these tables. 11. capsense constraints parameter min typ max units notes parasitic capacitance (c p ) of the capsense sensor 30 pf supply voltage variation (v dd ) 5% [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 28 of 43 12. electrical specifications 13. dc electrical characteristics 12.1 absolute maximum ratings parameter description min typ max unit notes t stg storage temperature ?55 25 +100 c higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c (0 c to 50 c). extended duration storage tempera- tures above 65 c degrade reliability t baketemp bake temperature ? 125 see package label c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied ?40 ? +85 c v dd supply voltage on v dd relative to v ss ?0.5 ? +6.0 v v io dc input voltage v ss ? 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tri-state v ss ? 0.5 ? v dd + 0.5 v i mio maximum current into any gpio pin ?25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd lu latch up current ? ? 200 ma 12.2 operating temperature parameter description min typ max unit notes t a ambient temperature ?40 ? +85 c t j junction temperature ?40 ? +100 c 13.1 dc chip le vel specifications parameter description min typ max unit notes v dd supply voltage 2.40 ? 5.25 v i dd supply current ? 1.5 2.5 ma conditions are v dd = 3.10 v, t a = 25 c [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 29 of 43 13.2 dc gpio specifications 13.4 dc flash write specifications this table lists guaranteed maximum and mini mum specifications for the voltage and tem perature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, 3.10 v to 3.6 v and ?40 c < t a < 85 c or 2.4 v to 2.90 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c. these are for design guidance only. flash endurance and retention specifications are va lid only within the range: 25 c20 c during the flash write operation. it is at the user?s own risk to oper ate out of this temperature range. if flash writing is done out of this temperatur e range, the endurance and data retention reduces. 13.2.1 5-v and 3.3-v dc gpio specifications this table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, 3.10 v to 3.6 v ?40 c t a 85 c. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. parameter description min typ max unit notes v oh1 high output voltage v dd ? 0.2 ? ? v i oh 10 a/pin, v dd 3.10 v v oh2 high output voltage v dd ? 0.9 ? ? v i oh = 1 ma/pin, v dd 3.10 v v ol low output voltage ? ? 0.75 v i ol = 20 ma/pin, v dd > 3.10 v, maximum of 40 ma sink current i oh high output current 0.01 ? 1 ma v dd 3.1 v i ol1 low output current on port 0 pins ? ? 10 ma v dd 3.1 v, maximum of 40 ma sink current c out capacitive load on pins as output 0.5 1.7 5 pf package and pin dependent. te m p = 2 5 c . 13.2.2 2.7-v dc gpio specifications this table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4 v to 2.90 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 2.7 v at 25 c and are for design guidance only. parameter description min typ max unit notes v oh1 high output voltage v dd ? 0.2 ? ? v i oh 10 a/pin v oh2 high output voltage v dd ? 0.5 ? ? v i oh = 0.2 ma/pin v ol low output voltage ? ? 0.75 v i ol = 10 ma/pin, maximum of 20 ma sink current i oh high output current 0.01 ? 0.2 ma v dd 2.9 v i ol1 low output current on port 0 pins ? ? 10 ma v dd 2.9 v, maximum of 20 ma sink current c out capacitive load on pins as output 0.5 1.7 5 pf package and pin dependent. te m p = 2 5 c . 13.3 dc por and lvd specifications parameter description min typ max unit notes v ppor0 v ppor1 v dd value for ppor trip v dd = 2.7 v v dd = 3.3 v, 5 v ? ? 2.36 2.60 2.40 2.65 v v v dd must be greater than or equal to 2.5 v during startup or reset from watchdog. symbol description min typ max units notes v ddiwrite supply voltage for flash write operations [7] 2.7 ? ? v i ddp supply current for flash write operations ? 5 25 ma flash enpb flash endurance 50,000 ? ? ? erase/write cycles flash dr flash data retention 10 ? ? years note 7. commands involving flash writes (0x01, 0x02, 0x03) and flas h read (0x04) must be executed only within the same v cc voltage range detected at por (power on, or command 0x06) and above 2.7 v. [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 30 of 43 13.5 dc i 2 c specifications this table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, 3.10 v to 3.6 v and ?40 c < t a < 85 c or 2.4 v to 2.90 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c. these are for design guidance only. 13.6 capsense electrical characteristics table 7. dc i 2 c specifications [9] symbol description min typ max units notes v ili2c input low level ? ? 0.3 v dd v 2.4 v v dd 3.6 v ? ? 0.25 v dd v 4.75 v v dd 5.25 v v ihi2c input high level 0.7 v dd ? ? v 2.4 v v dd 5.25 v v olp low output voltage ? ? 0.4 v i ol =5 ma/pin, maximum of 10 ma device sink current 2.4 v dd 2.9 v and 3.1 v dd 3.6 v. c i2c capacitive load on i 2 c pins 0.5 1.7 5 pf package and pin dependent. te m p = 2 5 c . r pu pull-up resistor 4 5.6 8 k notes 8. a maximum of 36 50,000 block endurance cycles is allowed. this is balanced between operations on 36 1 blocks of 50,000 ma ximum cycles each, 36 2 blocks of 25,000 maximum cycles each, or 36 4 blocks of 12,500 maximum cycles each (to limi t the total number of cycles to 36 50,0 00 and that no single block ever sees more than 50,000 cycles). 9. all gpio meet the dc gpio v il and v ih specifications found in the dc gpio specifications sections. the i 2 c gpio pins also meet the above specs . max (v) typ (v) min (v) conditions for supply voltage result 3.6 3.3 3.1 < 2.9 the device automatically reconfigures itself to work in 2.7 v mode of operation. > 2.9 or < 3.10 this range is not recommended for capsense usage. 2.90 2.7 2.45 < 2.45 v the scanning for capsense parameters shuts down until the voltage returns to over 2.45 v. > 3.10 the device automatically reconfigures itself to work in 3.3 v mode of operation. < 2.4 v the device goes into reset. 5.25 5.0 4.75 < 4.73 v the scanning for capsense parameters shuts down until the voltage returns to over 4.73 v. [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 31 of 43 14. ac electrical specifications 14.1 ac chip-level specifications 14.2 ac gpio specifications 14.2.1 5-v and 3.3-v ac gpio specifications 14.1.1 5-v and 3.3-v ac chip-level specifications parameter description min typ max units notes f 32k1 internal low-speed oscillator (ilo) frequency 15 32 64 khz calculations during sleep operations are done based on ilo frequency. t xrst external reset pulse width 10 ? ? us t powerup time from end of por to cpu executing code ? 150 ? ms sr power_ up power supply slew rate ? ? 250 v/ms 14.1.2 2.7-v ac chip-level specifications parameter description min typ max units notes f 32k1 internal low-speed oscillator (ilo) frequency 8 32 96 khz calculations during sleep operations are done based on ilo frequency. t xrst external reset pulse width 10 ? ? us t powerup time from end of por to cpu executing code ? 600 ? ms sr power_ up power supply slew rate ? ? 250 v/ms parameter description min max unit notes t rise rise time, strong mode, cload = 50 pf 15 80 ns v dd = 3.10 v to 3.6 v and 4.75 v to 5.25 v, 10% to 90% t fall fall time, strong mode, cload = 50 pf 10 50 ns v dd = 3.10 v to 3.6 v and 4.75 v to 5.25 v, 10% to 90% 14.2.2 2.7-v ac gpio specifications parameter description min max unit notes t rise rise time, strong mode, cload = 50 pf 15 100 ns v dd = 2.4 v to 2.90 v, 10% to 90% t fall fall time, strong mode, cload = 50 pf 10 70 ns v dd = 2.4 v to 2.90 v, 10% to 90% 14.3 ac i 2 c specifications parameter description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 kbps fast mode not supported for v dd < 3.0 v t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0 ? 0.6 ? s t lowi2c low period of the scl clock 4.7 ? 1.3 ? s t highi2c high period of the scl clock 4.0 ? 0.6 ? s t sustai2c setup time for a repeated start condition 4.7 ? 0.6 ? s [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 32 of 43 figure 12. definition of timing for fast/standard mode on the i 2 c bus t hddati2c data hold time 0 ? 0 ? s t sudati2c data setup time 250 ? 100 ? ns t sustoi2c setup time for stop condition 4.0 ? 0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ? 1.3 ? s t spi2c pulse width of spikes suppressed by the input filter ??050ns 14.3 ac i 2 c specifications (continued) parameter description standard mode fast mode units notes min max min max i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 33 of 43 15. examples of frequently used i 2 c commands sl. no. requirement i 2 c commands [10] comment 1 enter into setup mode w 00 a0 08 2 enter into normal mode w 00 a0 07 3 load factory defaults to ram registers w 00 a0 02 4 do a software reset w 00 a0 08 w 00 a0 06 ; enter into setup mode ; do software reset 5 save current configuration to flash w 00 a0 01 6 load factory defaults to ram registers and save as user configu- ration w 00 a0 08 w 00 a0 02 w 00 a0 01 w 00 a0 06 ; enter into setup mode ; load factory defaults to sram ; save the configuration to flash. wait for time specified in ta b l e 6 . ; do software reset 7 disable combinational logic output to dig0 w 00 1c 00 8 disable combinational logic output to dig1 w 00 21 00 9 clearing (logic 0) the both dig0 and dig1 outputs w 00 04 00 combinational logic output on dig0 and dig1 should be disabled before dong this operation (sl# 7 and 8) 10 setting (logic 1) the dig0 and clearing (logic 0) the dig1 outputs w 00 04 01 11 clearing (logic 0) the dig0 and setting (logic 1) the dig1 outputs w 00 04 02 12 setting (logic 1) the both dig0 and dig1 outputs w 00 04 03 13 change capsense clock to imo/2 w 00 a0 08 w 00 51 20 w 00 a0 07 ; enter into setup mode ; capsense clock is set as imo/2 ; enter into normal mode 14 change value of idac0 to ?x?h w 00 70 x ?x? represents new value of idac register 15 change value of idac1 to ?y?h w 00 71 y ?y? represents new value of idac register 16 change value of idac0 and idac1 to ?x?h and ?y?h w 00 70 x y ?x? and ?y? represents new value of idac register 17 change the value ft0 to ?x?h w 00 66 x ?x? represents new value of ft register 18 change the value ft1 to ?y?h w 00 67 y ?y? represents new value of ft register 19 change the value ft0 and ft1 to ?x?h and ?y?h w 00 66 x y ?x? and ?y? represents new value of ft registers 20 change noise threshold to ?x?h w 00 4e x 21 read capsense button cs0 scan results w 00 81 81 w 00 82 r 00 rd rd rd rd rd rd ; select capsense button for reading scan result ; set the read point to 82h ; consecutive 6 reads gets baseline, difference count and raw count (all two byte each) 22 read capsense button status register w 00 88 r 00 rd ; set the read pointer to 88 ; reading a byte gets status capsense inputs note 10. the ?w? indicates the write transfer and the next byte of data represents the 7-bit i2c address. the i2c address is assumed to be ?0? in the above examples. similarly ?r? indicates the read transfer followed by 7-bit address and data byte read operations. [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 34 of 43 16. ordering information note for die sales information, contact a local cypress sales office or field applications engineer (fae). 16.1 ordering code definitions thermal impedances solder reflow specifications ordering code package diagram package type operating temperature capsense blocks capsense inputs digital outputs xres pin cy8c20111-sx1i 51-85066 8-pin soic industrial yes 1 1 no cy8c20111-sx1it 51-85066 8-pin soic (tape and reel) industrial yes 1 1 no CY8C20121-SX1I 51-85066 8-pin soic industrial yes 2 2 no CY8C20121-SX1It 51-85066 8-pin soic (tape and reel) industrial yes 2 2 no cy marketing code: 8 = cypress semiconductors 8 c 201 xx - sx 1 i t tape and reel thermal rating : industrial 8 pin pinout package type : soic pb- free part number family code technology code: c = cmos company id: cy = cypress table 16-1. thermal impedance by package package typical ja [11] 8-pin soic 127.22 c/w table 16-2. solder reflow specifications package maximum peak temperature (t c ) maximum time above t c ? 5 c 8-pin soic 260 c 30 seconds note 11. t j = t a + power x ja. [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 35 of 43 17. package diagram figure 13. 8-pin (150-mil) soic (51-85066) 51-85066 *e [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 36 of 43 18. acronyms 18.1 acronyms used ta b l e 8 lists the acronyms that are used in this document. 19. document conventions 19.1 units of measure ta b l e 9 lists the units of measures. 19.2 numeric conventions hexadecimal numbers are represented with all letters in uppercase wi th an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimals. table 8. acronyms used in this datasheet acronym description acronym description ac alternating current lvd low voltage detect cmos complementary metal oxide semiconductor pcb printed circuit board crc cyclic redundancy check pga programmable gain amplifier csa capsense successive approximation por power on reset csd capsense sigma delta ppor precision power on reset dc direct current psoc ? programmable system-on-chip eeprom electrically erasable programmable read-only memory pwm pulse width modulator emc electromagnetic compatibility qfn quad flat no leads gpio general-purpose i/o slimo slow imo i/o input/output spitm serial peripheral interface idac current dac sram static random access memory ilo internal low speed oscillator srom supervisory read only memory imo internal main oscillator ssop shrink small-outline package lcd liquid crystal display usb universal serial bus ldo low dropout regulator wdt watchdog timer led light-emitting diode wlcsp wafer level chip scale package lsb least-significant bit xres external reset table 9. units of measure symbol unit of measure symbol unit of measure c degree celsius mm millimeter kbps kilo bits per second ms millisecond khz kilohertz na nanoampere k kilohm ns nanosecond lsb least significant bit % percent a microampere pf picofarad s microsecond v volts ma milliampere w watt [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 37 of 43 20. glossary active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opamp circuits. these are sc (switched capacitor) and ct (continuous time) blocks. these blocks can be interconnected to provide adcs, dacs, mu lti-pole filters, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. application programming interface (api) a series of software routines that comprise an interface between a computer application and lower level services and functions (for exampl e, user modules and libraries). apis serve as building blocks for programmers that create softwa re applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the positive temperature coefficient of vt with the negative temperat ure coefficient of vbe, to produce a ze ro temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specific ally as, for example, full width at half maximum. bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perfo rm one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for i/o operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and carrying similar data. typically represented using vector notation; fo r example, address[7:0]. 3. one or more conductors that serve as a co mmon connection for a group of related devices. clock the device that generates a periodic signal with a fixed frequen cy and duty cycle. a clock is sometimes used to synchroni ze different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 38 of 43 compiler a program that translates a high leve l language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in whic h the frequency is controlled by a piezoelectric crystal. typically a piezoelectric crystal is less sensitive to ambient te mperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data co mmunications, typically performed using a linear feedback shift register. similar calculations may be used for a variety of other purposes such as data compression. data bus a bi-directional set of signals used by a comp uter to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allo ws you to analyze the operation of the system under development. a debugger usually allows th e developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic blocks that can act as a counter, timer, se rial receiver, serial transmitter, crc generator, pseudo-random number generator, or spi. digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog- to-digital (adc) converter pe rforms the reverse operation. duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emul ation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc device. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of eproms, pl us in-system erasability. non-volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be pr otected. a flash block holds 64 bytes. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, vo ltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to connect low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control el ectronics. i2c uses only two bi-d irectional pins, clock and data, both running at +5v and pulle d high with resistors. the bus operates at 100 kbits/second in standard mode an d 400 kbits/second in fast mode. 20. glossary (continued) [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 39 of 43 ice the in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces da ta into or extracts data from a system. interrupt a suspension of a process, such as the ex ecution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code execution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exis t with its own priority and individual isr code block. each isr code block ends with the reti in struction, returning t he device to the point in the program where it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a ty pical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low-voltage detect (lvd) a circuit that senses v dd and provides an interrupt to the system when v dd falls lower than a selected threshold. m8c an 8-bit harvard-architecture microprocessor. the microprocessor coordinates all activity inside a psoc by interfacing to the fl ash, sram, and register space. master device a device that controls the timing for da ta exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external in terface. the controlled device is called the slave device . microcontroller an integrated circuit chip that is desi gned primarily for control systems and products. in addition to a cpu, a microcontroller typically includes memo ry, timing circuits, and i/o circuitry. the reason for this is to permit the realization of a co ntroller with a minimal quantity of chips, thus achieving maximal possible miniaturization. this in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or mo re characteristics of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation bet ween the logical inputs and outputs of the psoc device and their physical counterparts in t he printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. 20. glossary (continued) [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 40 of 43 port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the vo ltage is lower than a pre-set level. this is a type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and progra mmable system-on-chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware reset and software reset. rom an acronym for read only memory. a data-storage device from which data can be read out, but new data cannot be written in. serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register a memory storage device t hat sequentially shifts a word either left or right to output a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, th e slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. the controlling device is called the master device. sram an acronym for static random access memory. a memory device where you can store and retrieve data at a high rate of speed. the term static is used because, after a value is loaded into an sram cell, it remains unchanged until it is explicitly al tered or until power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is syn chronized by a clock signal. 20. glossary (continued) [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 41 of 43 tri-state a function whose output ca n adopt three states: 0, 1, and z (high-impedance). the function does not drive any value in the z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowin g another output to drive the same net. uart a uart or universal asynchronous receiver-tra nsmitter translates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardw are/firmware peripheral functions that take care of managing and configuring the lower level analog and digital psoc blocks. user modules also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the re gisters in this bank are more likely to be modified during normal program execution and not just durin g initialization. registers in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of time. 20. glossary (continued) [+] feedback
cy8c20111, cy8c20121 document number: 001-53516 rev. *g page 42 of 43 21. document history page document title: cy8c20111, cy8c20121 capsense ? express? - one button and two button capacitive controllers document number: 001-53516 rev. ecn no. orig. of change submission date description of change ** 2709248 slan/pyrs see ecn new data sheet *a 2821828 sshh/fsu 12/4/2009 - added contents - changed values in the registers table. - added the output_status register. - the note about flash writes must be performed at por voltage also applies to flash reads. - added new electrical specs incl uding tpowerup and output current. *b 2868929 slan 01/28/2010 converted from preliminary to final. updated package diagram. *c 2892629 njf 03/15/2010 added t baketemp and t baketime parameters in absolute maximum ratings . added the following tables: thermal impedance by package and solder reflow specifications . *d 3043236 arvm 09/30/10 removed f32ku and tpowerup rows from absolute maximum ratings table. included ?ac chip-level sp ecifications? section under ?ac electrical specifications? section *e 3087790 njf 11/16/10 removed section ?2.7-v dc spec for i2c line with 1.8 v external pull-up?. added dc i 2 c specifications table and dc programming specifications. updated units of measure, acronyms, and glossary sections. updated solder reflow specifications. no specific changes were made to i2c timing diagram. updated for clearer understanding. template and styles update. *f 3148656 arvm 01/20/11 in table under 9th section, deleted the 18th row (overlay thickness-buttons) in ?capsense constraints? table, de leted the 2nd row (overlay thickness) added following statement after table under 9th section - ?the recom- mended maximum overlay thickness is 2 mm. for more details refer to an53490, section: the integrating capacitor.? updated solder reflow specifications. *g 3287607 arvm 06/20/11 posting to external web. [+] feedback
document number: 001-53516 rev. *g revised june 24, 2011 page 43 of 43 capsense express?, psoc designer?, and programmable system-on-chip? are trademarks and psoc? is a registered trademark of cypre ss semiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i 2 c components from cypress or one of its sublicense d associated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c20111, cy8c20121 ? cypress semiconductor corporation, 2009-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. 22. sales, solutions , and legal information 22.1 worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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